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X2apic

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Title: X2apic  
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Subject: CPUID, Intel Inboard 386, Intel TeraHertz, MMC-1, Intel Communication Streaming Architecture
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X2apic

x2APIC is the most recent generation of the Intel programmable interrupt controller, introduced with the Nehalem microarchitecture.[1] The major improvements of the x2APIC address the number of supported CPUs and performance of the interface.

Contents

  • Features 1
  • Virtualization-related developments 2
  • See also 3
  • References 4
  • External links 5

Features

The x2APIC now uses 32 bits to address CPUs, allowing to address up to 2^32-1 CPUs using the physical destination mode. The logical destination mode now works differently and introduces clusters. Using this mode, one can address up to 2^20-16 processors.

The x2APIC architecture also provides backward compatibility modes to the original Intel APIC Architecture (introduced with the Pentium/P6) and with the xAPIC architecture (introduced with the Pentium 4).

The improved interface reduces the number of needed APIC register access for sending Inter-processor interrupts. Because of this advantage Qemu can and does emulate x2apic for older processors that don't physically support x2APIC, going back to Conroe and even for AMD Opteron G-series processors (neither of which natively support x2APIC).[2][3]

Virtualization-related developments

As of 2012 AMD does not yet support x2APIC, but was announcing the introduction of their own Advanced Virtual Interrupt Controller (AVIC) targeting interrupt overhead reduction in virtualization environments.[4][5]

Intel has responded with the announcement of a similar technology, which didn't have a brand name at its announcement time in 2012,[6] but which was later branded APICv[7][8] and is commercially available in the Ivy Bridge EP series, which is sold as Xeon E5-26xx v2 (launched in late 2013) and as Xeon E5-46xx v2 (launched in early 2014).

See also

References

  1. ^ "Next Generation Interrupt Architecture"
  2. ^ https://lists.gnu.org/archive/html/qemu-devel/2013-07/msg03756.html
  3. ^ http://lists.nongnu.org/archive/html/qemu-devel/2014-01/msg02441.html
  4. ^ Wei Huang, Introduction of AMD Advanced Virtual Interrupt Controller, XenSummit 2012
  5. ^ http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-interrupt-virt-kvm-roedel.pdf
  6. ^ http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-intel-vt-feat-nakajima.pdf
  7. ^ https://software.intel.com/en-us/blogs/2013/12/17/apic-virtualization-performance-testing-and-iozone
  8. ^ http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-e5-4600-v2-brief.pdf

External links

  • Intel 64 Architecture x2APIC Specification (PDF)
  • More information on the Intel x2APIC Architecture can be found in the Intel 64 and IA-32 Architectures Software Developer's Manuals


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